1. Field of the Invention
The present invention relates to electrically erasable and programmable read only memory (EEPROM) cells, and more particularly to single poly EEPROM memory cells and an array using such cells in which the cells are connected to provide a faster read and write performance with reduced product term coupling.
2. Description of the Prior Art
Single poly EEPROM cells are known in the prior art and arrays using such cells are also known. Typical prior art circuits are illustrated in FIGS. 1 and 2. Referring to FIG. 1, the cell disclosed therein was described in an IEEE paper entitled "A Family of High Performance CMOS Programmable Logic Devices Using a Single Polysilicon Electrically Erasable Floating Gate Cell" by John Turner, presented at the 10th IEEE Non-Volatile Workshop, Aug. 14-16, 1989. Referring to FIG. 1, the Turner memory cell is comprised of memory transistor MC1, write transistor TW1 and read transistor TR1. Memory transistor MC1 of FIG. 1 is of the single poly type, that is, only the floating gate of polycrystalline silicon is utilized, and the control gate consists of a diffusion in the substrate below the floating gate. The write gate (WG) is effectively a portion of a diffusion of write transistor TW1, which is of course also in the substrate. It will be appreciated by reference to FIG. 1, that the select gate for both the write and read transistors are commonly connected to select line SL1. When performing either a write or read operation, the potential is provided to the select gates over select line SL1 with appropriate potentials being applied to the other terminals of the cell. When the cell is utilized in its typical environment, which is as part of a large array of cells, each of the select gates in a row of memory cells are commonly connected to the select line for that row. Since all of the select gates for the write and read transistors in a row are coupled to the same line, a significant amount of capacitance is seen by the select line and accordingly when either a write or a read operation is to be performed, a delay in its performance results because of the significant amount of capacitance which results from having all of the select gates coupled to the same line.
Another single poly EEPROM cell is schematically illustrated in FIG. 2. This cell was reported on in a paper entitled "A 20 ns CMOS Programmable Logic Device for Asynchronous Applications", by Jagdish Pathak et al. in the 9th IEEE Non-Volatile Semiconductor Memory Workshop, Feb. 22-24, 1988 in Monterey, Calif. Referring to FIG. 2, the Pathak et al. cell includes memory cell transistor MC2, write transistor TW2 and read transistor TR2. In the memory cell illustrated in FIG. 2, the select gates of both the write transistor and read transistor are commonly connected to select line SL2. Thus it will be apparent by comparison of the schematics in FIG. 1 and FIG. 2, that the select gates for the cells are commonly connected. Accordingly, when a read or a write operation is to be performed, appropriate potential is applied to select line SL2, and potentials are applied to other terminals of the cell at the required levels to perform either a read or a write operation. Memory cell in FIG. 2 suffers from the same operational problems associated with the cell in FIG. 1 with respect to speed. Since all of the select gates on a row are commonly coupled, a speed degradation problem occurs in the same manner as described above with respect to the circuit of FIG. 1.
Other disadvantages of prior art single poly EE cells reside in the manner in which the first and second level metals are connected to the product term terminals of the read and write transistors and the connection from the select gates and the metallization to which the select gates are connected. More particularly, in prior art devices the second level metal is connected to the select gates and straps are used between the second level metal and the select gates at periodic intervals to provide reduced resistance in the select gate path. The first level metal in a prior art cell of this type is connected to the product term terminals of the cell (WRITE PT and READ PT). This utilization of first and second level metals results in what is known as the "sandwich effect" since the second metal (which is of course above the first level metal) and the poly select gates which are below the first level metal effectively result in a sandwich of those two conductors on opposite sides of the first level metal. This "sandwich" construction adds additional row to product term capacitance in the select lines which results in a slower speed read operation. Additionally, since first level metal is used for connection to the product term terminals, the relative proximity between first level metal and the substrate results in capacitance which decreases the speed with which a read operation may be performed when contrasted to the present invention in which second level metal is used for the product terms.
Another cell of the prior art is described in a paper entitled "A High Performance CMOS EEPAL Cell" by Nader Radjy et al. which was presented at the 9th IEEE Non-Volatile Semiconductor Memory Workshop, held Feb. 22-24, 1988 in Monterey, Calif. The cell described in the paper differs from the cell of the present invention in that the cell described in the paper is a double poly cell, and secondly, first level metal is utilized for connections to the product term terminals. The latter construction of course results in the undesirable increase in capacitance described above. Additionally, although the Radjy et al. description indicates that a separate select line is utilized for read and write select gates, since the cell is double poly, it is significantly more complicated to manufacture.